3-20 Heavy Ion Induced Single Event Upset in a Harden SOI SRAM-中国期刊网

摘要 Inordertodeepentheunderstandingofthedifferencebetween0!1and1!0sinleeventupset(SEU)cross-sectioninanovelactivedelayelement(ADE)SRAM(StaticRandomAccessMemory)cell,theirradiationwascarriedoutatHeavyIonResearchFacilityinLanzhou(HIRFL).Usingthe86Kr26+ionsirradiatedthedeviceundertest(DUT)adoptedpartiallydepleted(PD)siliconofinsulator(SOI)technology.ThefeaturesizeofDUTfabricatedbyinstituteofmicroelectronic(IME)was180nm.TheschematicdiagramofSEUhardenADE-SRAMcellisshowninFig.1.TheADEisessentiallyaNMOSconnectedinonlyoneofthefeedbackpathsbetweenthetwoinventorsofthememorycell.Itplaysaroleasswitchingtransistor.Exceptduringawriteoperation,whentheswitchtransistoristurnedon(soasnottocompromisethewritespeed),theoff-ADEprovidesamuchgreaterRCdelaybetweenthetwoinventorsofthememorycelltoachievemuchimprovedSEUhardness[1].

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3-20 Heavy Ion Induced Single Event Upset in a Harden SOI SRAM

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3-20 Heavy Ion Induced Single Event Upset in a Harden SOI SRAM

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